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Job Description: 1. Responsible for SOC chip-level and sub-system level integration task. 2. SOC/sub-system hierarchical architecture plan, RTL design rule check, RTL synthesis, equivalent check, timing sign-off, timing ECO, low power design rule check, performance/power/area quality boost, and etc. 3. Support chip-level/sub-system physical implementation, including floorplan, power plan, placememt, clock tree synthesis, routing, LVS/DRC, and etc. Job requirements: 1. MSEE degree or above in microelectronics, computer, electronic engineering, communication engineering, and other related fields. 2. Familiar with Verilog and ASIC front-end design flow, with solid digital circuit theory foundation, hands-on ability and innovation ability. 3. Professional in IC EDA tools(such as Spyglass/Genus/DC/PT/LEC/CLP/DFTC/TestMax/Tessent/Innovus/ICC and etc), and with ASIC design experience, such as RTL coding, Synthesis, P&R, STA timing sign-off, IR Analysis Post-silicon diagnosis and etc. 4. Familar with scripting language, such as Makefile/Tcl/Perl/Python, and etc. 5. Good communication and team-work skills, good English communication and presentation experience. 6. Passion work attitude, full of curiosity about technology, courage to take responsibility, and able to work under strong pressure. Work location: 合肥Hefei (MHF site) Required seniority of this role: 1. 3+ years SOC digital design/integration/physical design related experience.